{"id":382,"date":"2026-09-24T00:32:29","date_gmt":"2026-09-24T08:32:29","guid":{"rendered":"https:\/\/brentpeters.me\/wiki\/?post_type=knowledgebase&p=382"},"modified":"2026-09-24T00:38:25","modified_gmt":"2026-09-24T08:38:25","slug":"self-triggered-photonic-logic-clockless-gating-and-the-end-of-timing-side-channels","status":"publish","type":"knowledgebase","link":"https:\/\/brentpeters.me\/wiki\/knowledge-base\/research\/self-triggered-photonic-logic-clockless-gating-and-the-end-of-timing-side-channels\/","title":{"rendered":"Self-Triggered Photonic Logic: Clockless Gating and the End of Timing Side Channels"},"content":{"rendered":"

Companion to “The Dawn of Optical Computing: Photonic Analog Computing and Emergent Hardware Security”. Made with the help of AI.<\/em><\/p>\n

The Gap in the Resonance Model<\/h2>\n

The distributed photonic subroutine architecture establishes a powerful claim: security emerges when logic is instantiated in physical substrates rather than symbolic layers. A downstream circuit initializes only if upstream analog logic produces the correct resonant state. This is elegant\u2014and it leaves one question open.<\/p>\n

When does a module fire?<\/strong><\/p>\n

In purely resonant systems, the answer is implicit: continuously, at the clock rate of the driving laser or the repetition rate of the pulse train. Every module is always live. Every pathway is always probing. This creates three residual vulnerabilities that even physics-bound computation inherits:<\/p>\n

    \n
  1. Static power signature.<\/strong>\u00a0Idle modules still bias, still heat, still emit. The power trace reveals which subroutines exist in the topology, even when no valid input flows.<\/li>\n
  2. Timing predictability.<\/strong>\u00a0If activation follows a global optical clock or pulse repetition interval, an attacker with access to electromagnetic emanation can reconstruct the execution schedule without ever touching the data path.<\/li>\n
  3. Resonance spoofing by saturation.<\/strong>\u00a0A sufficiently strong broadband source can force every tuning fork to vibrate simultaneously\u2014not by matching the correct frequency, but by overwhelming the discrimination margin.<\/li>\n<\/ol>\n

    These are not software attacks. They are\u00a0physics attacks on physics-based security<\/em>. And they share a single root cause:\u00a0the system knows when it is supposed to compute.<\/strong><\/p>\n

    The Fix: Remove the Clock Entirely<\/h2>\n

    Threshold triggering replaces scheduled activation with signal-activated activation. A photonic vat\u2014a charge well, a cavity, a slow-light buffer\u2014advances its contents downstream\u00a0only when the accumulated input crosses a physical threshold<\/strong>. Not when a clock edge says so. Not when the pulse train arrives. When the physics demands it.<\/p>\n

    Comparison of Activation Models:<\/strong><\/p>\n

      \n
    • Clocked photonic logic:<\/strong>\u00a0Laser pulse triggers all modules to sample and propagate simultaneously.<\/li>\n
    • Self-triggered photonic logic:<\/strong>\u00a0Signal accumulates until threshold is crossed, then triggers a cascade. No global time reference exists.<\/li>\n<\/ul>\n

      This converts the Peters model’s “physical continuity validation” from a\u00a0state test<\/em>\u00a0into a\u00a0rate test<\/em>. The downstream module doesn’t just check whether the upstream resonance has the right frequency\u2014it checks whether the upstream computation produced enough coherent energy, fast enough, to justify activation. An artificially induced resonance that lacks the correct temporal envelope fails this second gate.<\/p>\n

      Four Security Properties That Emerge<\/h2>\n

      1. Power Analysis Becomes Meaningless<\/h3>\n

      A clocked photonic FFT chip\u2014even a fully analog one\u2014draws current in lockstep with its clock. Bin activations appear as periodic bumps in the power trace; an attacker correlates bump patterns to input classes. This is textbook side-channel extraction, and it works against analog hardware because analog hardware still runs on clocks.<\/p>\n

      A self-triggered system has no such rhythm. Power consumption tracks the\u00a0signal envelope<\/strong>, not the algorithm schedule. Quiet inputs produce quiet chips. The attacker cannot distinguish “empty channel” from “encrypted payload” from “processing idle frames,” because the hardware itself cannot distinguish them either. The information simply isn’t there to extract.<\/p>\n

      Why Power Analysis Fails:<\/strong>\u00a0In clocked systems, the attacker recovers the bin schedule. In self-triggered systems, the attacker sees only signal amplitude, with no clock phase to reconstruct and no duty-cycle inference possible because load is signal-dependent by design.<\/p>\n

      2. Saturation Attacks Fail Gracefully<\/h3>\n

      Overwhelming a resonant filter bank with broadband noise forces false positives\u2014the forks ring whether struck correctly or hammered indiscriminately. Threshold triggering adds a\u00a0temporal coherence requirement<\/strong>: the threshold must be crossed within a defined integration window, which only genuine signal achieves. Noise spreads energy across many bins slowly; a valid subroutine output concentrates it sharply. The vat fills too slowly under attack conditions, and the cascade never starts.<\/p>\n

      The system degrades to\u00a0silence<\/em>\u00a0under saturation, not to\u00a0false acceptance<\/em>.<\/p>\n

      3. Fault Injection Loses Its Target<\/h3>\n

      Clock glitching is the workhorse of hardware fault injection: disturb the clock, freeze or skip a cycle, observe erroneous outputs for differential cryptanalysis. A self-triggered architecture has no clock to glitch. Fault injection must instead corrupt the signal directly\u2014which means injecting energy into the optical path, where the perturbation propagates through the same physical continuity checks the architecture already enforces. The defense and the computation become the same mechanism.<\/p>\n

      4. Topology Hides in Activity Patterns<\/h3>\n

      In the distributed subroutine graph, attackers who can observe which modules activate learn the program structure. Self-triggering scrambles this: activation order depends on input statistics, not call graph. Two identical inputs arriving at different amplitudes traverse different temporal paths through the network. The topology is real but temporally opaque\u2014an attacker sees a flickering pattern that averages to nothing useful.<\/p>\n

      Implementation Sketch: The Photonic Vat Chain<\/h2>\n

      Concretely, the building block maps directly onto existing components. The stage consists of:<\/p>\n

        \n
      • Integration cavity:<\/strong>\u00a0A slow-light waveguide or high-Q resonator that accumulates incoming optical intensity.<\/li>\n
      • Nonlinear threshold element:<\/strong>\u00a0A component such as two-photon absorption, carrier-dispersion switch, or quantum-dot saturable absorber that fires when stored energy exceeds a set voltage threshold.<\/li>\n
      • Release mechanism:<\/strong>\u00a0The firing event releases the stored packet into the next stage and generates the local gate signal for the current stage’s readout.<\/li>\n
      • Self-timed reset:<\/strong>\u00a0An auxiliary bleed waveguide resets the cavity, timed by the firing event itself.<\/li>\n<\/ul>\n

        There is no electrical clock distribution and no global synchronization. The cascade propagates at whatever speed the signal supports, and stops entirely when signal stops. For the analog FFT application, each “vat” becomes a dispersive delay cell whose advance triggers the next correlation stage\u2014producing spectra only when measured, consuming nothing when silent.<\/p>\n

        What This Adds to the Peters Interpretation<\/h2>\n

        The original framework concludes that “the safest computation is the one most tightly bound to its physical substrate.” Self-triggering sharpens this into an operational principle:<\/p>\n

        The safest computation is also the one that can decide for itself when to happen.<\/strong><\/p><\/blockquote>\n

        Resonance answers\u00a0what<\/em>\u00a0is computing. Threshold answers\u00a0whether<\/em>\u00a0and\u00a0when<\/em>. Together they close the last abstraction gap\u2014the assumption that some external scheduler owns time. In digital systems, the clock is the root authority, and everything downstream of it is attackable. In self-triggered photonic logic, time is generated locally by the signal itself. There is no authority upstream of the physics to compromise.<\/p>\n

        Security remains emergent. But now it emerges along the time axis as well as the spatial one.<\/p>\n","protected":false},"excerpt":{"rendered":"

        Companion to “The Dawn of Optical Computing: Photonic Analog Computing and Emergent Hardware Security”. Made with the help of AI. The Gap in the Resonance Model The distributed photonic subroutine architecture establishes a powerful claim: security emerges when logic is instantiated in physical substrates rather than symbolic layers. A downstream circuit initializes only if upstream […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","template":"","knowledgebase_cat":[16],"class_list":["post-382","knowledgebase","type-knowledgebase","status-publish","hentry","knowledgebase_cat-research"],"yoast_head":"\nSelf-Triggered Photonic Logic: Clockless Gating and the End of Timing Side Channels<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/brentpeters.me\/wiki\/knowledge-base\/research\/self-triggered-photonic-logic-clockless-gating-and-the-end-of-timing-side-channels\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Self-Triggered Photonic Logic: Clockless Gating and the End of Timing Side Channels\" \/>\n<meta property=\"og:description\" content=\"Companion to “The Dawn of Optical Computing: Photonic Analog Computing and Emergent Hardware Security”. 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